There are probably other ways to attack the problem as well. This can be done in a process where a N-type buried layer (or tub) is added to provide an isolation well. Another way to do it is to have the NFET inside a well. One way is to eliminate the common substrate completely, as is done in Silicon On Insulator (SOI). There are ways around this limitation for NFETs. In linear circuits, such as a cascode amplifier or differential pair, you will start to see this effect, but it also depends on how sensitive the process is to bulk voltages. Most digital gates I've seen just use a common N-well for the PFETs for space and performance reasons. For digital CMOS logic, this is often neglected because an "on" chain will have a small bulk-source voltage. The impact is that the higher your NFET source voltage (relative to the substrate), the lower your drain current for a given Vgs. This is one of the simplist ways of making a CMOS process. It forms a diode to the substrate (N-type well to P-type substrate) that is reverse-biased (off) as long as the well voltage is positive. Since this well is an added feature, you can place it wherever you want. To get PFETs in the same circuit, they need to add N-type wells to the substrate. This allows NFETs to be built directly in the substrate without "extra" steps. Perhaps looking at it another way, a traditional bulk CMOS process is built on a P-type wafer.
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